1. Field of the Invention
The present invention relates to a thin-film transistor (TFT) and, more particularly, to a method for manufacturing a TFT that can reduce the number of photolithography processes, that can easily adjust a width of an lightly doped drain region and planarize the film surface.
2. Description of the Related Art
Generally, TFTs are widely used as a switching element for turning On/Off pixels of a flat panel display such as an active matrix liquid crystal display, because they can contain CMOS on the substrate. To use the TFT as a switching element, the TFT should be able to withstand a high voltage and to provide a high ratio of On currents to Off current.
As is well known, such a TFT is manufactured through a number of photolithography processes, each comprising a plurality of steps such as a photoresist step, a light-exposing step, and an etching step. As the number of processes increases, the overall productivity is lowered and the quality of the TFT is deteriorated.
In addition, in the conventional TFT, since source and drain electrodes and a gate electrode are formed in a different step, it is difficult to adjust the width of an lightly doped drain (LDD) region, while increasing the number of layers that are stacked and the number of photolithography processes. The more number of layers stacked makes a surface of the TFT uneven, costing the reflecting efficiency in a reflective-type LCD.
Therefore, the present invention has been made in an effort to solve the above described problems.
It is an objective of the present invention to provide a method for manufacturing a TFT that can reduce the number of photolithography processes, that can easily adjust the width of an LDD region and planarize the TFT surface.
To achieve the above objective, the present invention provides a method for manufacturing a thin film transistor comprising the steps of forming a channel region on a surface of a substrate, depositing an insulating layer on the surface of the substrate while covering the channel region and patterning the insulating layer such that a portion of the channel region is exposed, depositing a silicon layer on the insulating layer, depositing a metal layer on the silicon layer and etching the silicon and metal layers to define source, drain and gate electrode sections, doping positive ions on a portion corresponding to a MOS circuit portion, depositing an intermediate insulating layer on the metal layer while covering the source, drain and gate electrode sections and patterning the intermediate insulating layer to form a plurality of contact holes, and depositing an electrode material on the intermediate insulating layer and patterning the electrode material to define a pixel electrode section and a wire section.
The method may further comprise the step of doping negative ions to define an LDD region at an exposed portion of the channel region before doping the positive ions.
The step of doping the positive ions comprises the step of doping n+ ions of on an NMOS circuit section. Alternatively, the step of doping the positive ions comprises the step of doping p+ ions on a PMOS circuit section.